It is a verification methodology, based on a class library defined using syntax and semantics of IEEE 1800, SystemVerilog HDL. Thus it is a SystemVerilog based verification methodology
The UVM is a standard created by the Accellera standards group and is open to the whole electronics industry.
What are the benefits of UVM?
UVM is supported by all leading simulation/verification tools vendors, making the verification environments portable across different verification tools. As Verification IP (VIP) providers build their IP based on UVM, the reuse of verification environment will increase, causing improved productivity of verification engineers and improved quality of the designs.(http://www.uvmworld.org)
The UVM Verification Reference App (UVM Ref) can use the possibilities which mobile phone brings so you have all the most useful UVM syntax on the go.
Do you have a job interview or do you want to improve your verification programming skills (system verilog, e language - specman, systemC )?
study on the transportation instead of wasting your time and become an UVM Guru.
Where can I find the UVM standard? How can I learn more about UVM?
UVM standard is available at www.accellera.org. Here you can find the standard (UVM 1.1 Class Reference), the reference implementation (tarball) and User's Guide. There is also a link to discussion forum, and instructions on how to provide feedback. If you wish to be a regular participant in the development of UVM, you should also join VIP-TSC (www.accellera.org/activities/vip).
The UVM Verification Reference App is currently BETA meaning there are terms from the standard which needs to be added or fixed.
Your prompt feedback would be highly appreciated.
Thanks list for the bugs finders:
*The app is targeted for ASIC / VLSI / VHDL / VERILOG / SYSTEM VERILOG / E (specman) / VERA / SYSTEMC /
PSL / VMM / OVM / UVM - Verification engineers.
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Fix for UVM videos