by: Guosheng Wu • 1
Robei is the world smallest EDA tool for FPGA design and simulation. With this tool, you can design your hardware visually in both RTL level and behavior level at anywhere, and view the simulation result through waveform. It is a tiny, fast software for hardware prototyping and verification.
Robei has modern GUI, Verilog compiler, property editor, code viewer and waveform viewer. The modern user interface of Robei provides visualization of FPGA design and simplified it by playing with reusable models and ports. The Toolbox is designed to contain huge of model libraries, and no matter where is your models. Property designer offers the most convenient method for viewing and changing values in code. All these parts are designed to be as simple as possible. As long as you familiar with Verilog language, you can manage it in 15 minutes.
You need to install Ministro, which is a free application from google market. And the document on windows platform locates at :http://robei.com/Software/help.pdf, although there is some difference, but most of the part are same. If you have an problem in using Robei, please contact me at firstname.lastname@example.org for support.
Tags: verilog , robei , for verilog , verilog design on amdroid , robeiproblem , verilog viewer , verilog vcd , verilog code viewer , verilog compiler